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Low-, medium- and high-density reset and clock control (RCC)
Bit 10 SDIOEN: SDIO clock enable
Set and cleared by software.
0: SDIO clock disabled
1: SDIO clock enabled
RM0008
Bits 9
Reserved, always read as 0.
Bit 8 FSMCEN: FSMC clock enable
Set and cleared by software.
0: FSMC clock disabled
1: FSMC clock enabled
Bit 7
Reserved, always read as 0.
Bit 6 CRCEN: CRC clock enable
Set and cleared by software.
0: CRC clock disabled
1: CRC clock enabled
Bit 5
Reserved, always read as 0.
Bit 4 FLITFEN: FLITF clock enable
Set and cleared by software to disable/enable FLITF clock during sleep mode.
0: FLITF clock disabled during Sleep mode
1: FLITF clock enabled during Sleep mode
Bit 3
Reserved, always read as 0.
Bit 2 SRAMEN: SRAM interface clock enable
Set and cleared by software to disable/enable SRAM interface clock during Sleep mode.
0: SRAM interface clock disabled during Sleep mode.
1: SRAM interface clock enabled during Sleep mode
Bit 1 DMA2EN: DMA2 clock enable
Set and cleared by software.
0: DMA2 clock disabled
1: DMA2 clock enabled
Bit 0 DMA1EN: DMA1 clock enable
Set and cleared by software.
0: DMA1 clock disabled
1: DMA1 clock enabled
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Doc ID 13902 Rev 9
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